1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a gate contact structure for a semiconductor device and the resulting device structures.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
In contrast to a planar FET, which, as the name implies, is a generally planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, a sidewall spacer 18 and a gate cap layer 20. Trenches 22 are formed in the substrate 12 to define the fins 14. A recessed layer of insulating material (not shown) is positioned under the gate structure 16 and between the fins 14 in the areas outside of the gate structure, i.e., in the source/drain regions of the device 10. The gate structure 16 is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The gate structures 16 for such FinFET devices 10 may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques. A FinFET device may have either a tri-gate or dual-gate channel region. For a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior FET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years, particularly the channel length of transistor devices. As a result of the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections or “wiring arrangement” for the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured. Accordingly, the various electrical connections that constitute the overall wiring pattern for the integrated circuit product are formed in one or more additional stacked so-called “metallization layers” that are formed above the device level of the product. These metallization layers are typically comprised of layers of insulating material with conductive metal lines or conductive vias formed in the layers of material. Generally, the conductive lines provide the intra-level electrical connections, while the conductive vias provide the inter-level connections or vertical connections between different levels. These conductive lines and conductive vias may be comprised of a variety of different materials, e.g., copper, with appropriate barrier layers, etc. The first metallization layer in an integrated circuit product is typically referred to as the “M1” layer, while the conductive vias that are used to establish electrical connection between the M1 layer and lower level conductive structures (explained more fully below) are typically referred to as “V0” vias. The conductive lines and conductive vias in these metallization layers are typically comprised of copper, and they are formed in layers of insulating material using known damascene or dual-damascene techniques.
FIG. 1B is a cross-sectional view of an illustrative integrated circuit product 10A comprised of a plurality of transistor devices 15 formed in and above a semiconductor substrate 12A. A schematically depicted isolation region 13 has also been formed in the substrate 12A. In the depicted example, the transistor devices 15 are comprised of an illustrative gate structure, i.e., a gate insulation layer 15A and a gate electrode 15B, a gate cap layer 21, a sidewall spacer 23 and simplistically depicted source/drain regions 25. At the point of fabrication depicted in FIG. 1B, layers of insulating material 17A, 17B, i.e., interlayer dielectric materials, have been formed above the product 10A. Other layers of material, such as contact etch stop layers and the like, are not depicted in the attached drawings. Also depicted are illustrative raised epi source/drain regions 25X and source/drain contact structures 27 which include a combination of a so-called “trench silicide” (TS) structure 29 and a so-called “CA contact” structure 31. Also depicted is a gate contact structure 33 which is sometimes referred to as a “CB contact” structure. The CB contact 33 is formed so as to contact a portion of the gate electrode 15B of one of the transistors 15. In a plan view, the CB gate contact 33 is positioned vertically above the isolation region 13 that surrounds the product 10A, i.e., the CB gate contact 33 is not positioned above the active region defined in the substrate 12A. The CA contact structures 31 may be in the form of discrete contact elements, i.e., one or more individual contact plugs having a generally square-like or cylindrical shape, that are formed in an interlayer dielectric material, as shown in FIG. 1B. In other applications (not shown in FIG. 1B), the CA contact structures 31 may also be a line-type feature that contacts underlying line-type features, e.g., the TS structure 29 that contacts the source/drain region 25, 25X and typically extends across the entire active region on the source/drain region 25.
Also depicted in FIG. 1B is the first metallization layer—the so-called M1 layer—of the multi-level metallization system for the product 10A that is formed in a layer of insulating material 35, e.g., a low-k insulating material. A plurality of conductive vias—so-called V0 vias 37—are provided to establish electrical connection between the device-level contacts—CA contacts 31 and the CB contact 33—and the M1 layer. The M1 layer typically includes a plurality of metal lines 39 that are routed as needed across the product 10A.
In one embodiment, the process flow of forming the TS structures 29, CA contacts 31 and CB contacts 33 may be as follows. After the first layer of insulating material 17A is deposited, TS openings are formed in the first layer of insulating material 17A that expose portions of underlying source/drain regions 25, 25X. Thereafter, traditional silicide is formed through the TS openings, followed by forming tungsten (not separately shown) on the metal silicide regions, and performing a chemical mechanical polishing (CMP) process down to the top of the gate cap layer 21. Then, the second layer of insulating material 17B is deposited and contact openings for the CA contacts 31 are formed in the second layer of insulating material 17B that expose portions of the underlying tungsten metallization above the source/drain regions 25. Next, while the opening for the CA contacts 31 is masked, the opening for the CB contact 33 is formed in the second layer of insulating material 17B and through the gate cap layer 21 so as to expose a portion of the gate electrode 15B. Typically, the CB contact 33 is in the form of a round or square plug. Thereafter, the conductive CA contacts 31 and the conductive CB contact 33 are formed in their corresponding openings in the second layer of insulating material 17B by performing one or more common metal deposition and CMP process operations, using the second layer of insulating material 17B as a polish-stop layer to remove excess material positioned outside of the contact openings. The CA contacts 31 and CB contact 33 typically contain a uniform body of metal, e.g., tungsten, and may also include one or more metallic barrier layers (not shown) positioned between the uniform body of metal and the layer of insulating material 17B. The source/drain contact structures 27 (TS contacts 29, CA contacts 31) and the CB contact 33 are all considered to be device-level contacts within the industry.
FIG. 1C is a simplistic plan view of an illustrative FinFET device comprised of three illustrative fins 41. Also depicted are illustrative CA contacts 31, a CB contact 33, a gate cap layer 21, a sidewall spacer 23 and the trench silicide structures 29 formed above the source/drain regions 25. As noted above, the CB gate contact 33 is positioned vertically above the isolation region 13 that surrounds the product 10A, i.e., the CB gate contact 33 is not positioned above the active region defined in the substrate 12A. The CB gate contact 33 is positioned above the isolation region 13 so as to avoid or reduce the chances of creating an electrical short between the CB contact 33 and the TS structure 29, i.e., there is a minimum spacing 43 that must be maintained between these two structures according to various design rules in an attempt to prevent such electrical shorts. Unfortunately, there is an area penalty associated with the requirement that the CB contact 33 only be positioned above the isolation region 13 and maintaining a minimum value for the spacing 43. The problem is the same for transistor configurations other than FinFET devices as well, e.g., planar FET devices. What is needed is a method for forming the CB gate contact 33 above the active region of the device so as to conserve valuable plot space on an integrated circuit product.
The present disclosure is directed to various methods of forming a gate contact structure for a semiconductor device and the resulting device structures that may avoid, or at least reduce, the effects of one or more of the problems identified above.